Implement CPU in FPGA. Core SomeAVR on verilog

In this article I try to talk about implementation part of CPU that can execute instructons subset of original AVR core. It’s only preview and can be use for academic using only. Because most useful programm that this CPU can execute is LED blinking 🙂 You can view this in following video:

Here right 8 LEDs indicate value of register R20. Left 8 LEDs – value of IP(PC).
I found several implementations of AVR core in FPGA: pAVR, AVR Core, Navré AVR clone. But all of them is very complicated and some of them written not on Verilog. But I want learn only Verilog now. Most similar project is reducedAVR. But m4k ram blocks is much simplier than UFM.
Now implemented following instructions: some of arithmetic and branch on condition. Code that execution by CPU in previous video:

Source code of SomeAVR you can found on github. Sorry for generated by Quartus trash files.

On load programm on FPGA all registers reseted to default value/ You can view this in next video: