Попытка написать UART передатчик на 115200 бод. Страшно конечно, но вроде работает :-). Не стреляйте в пианиста — он играет, как умеет. Ниже исходник:
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module cyc_03 ( input wire clk, output reg hz_1, output reg hz_115200, output reg tx ); reg [24:0]counter_hz1 = 0; reg [24:0]counter_hz115200 = 0; reg [7:0]uart_data = 8'd48; reg [3:0]state = 4'd15; reg [3:0]letter = 0; always @(posedge clk) begin //1 HZ generator if(counter_hz1 == 25'd25000000) begin counter_hz1 <= 25'd0; hz_1 <= ~hz_1; end else counter_hz1 <= counter_hz1 + 1'd1; //UART generator if(counter_hz115200 == 25'd217) begin counter_hz115200 <= 25'd0; hz_115200 <= ~hz_115200; end else counter_hz115200 <= counter_hz115200 + 1'd1; end always @(posedge hz_115200) begin case(state) 0: if(hz_1) state <= state + 1'd1; 1: begin tx <= 1'd0; state <= state + 1'd1; end 2: begin tx <= uart_data[0]; state <= state + 1'd1; end 3: begin tx <= uart_data[1]; state <= state + 1'd1; end 4: begin tx <= uart_data[2]; state <= state + 1'd1; end 5: begin tx <= uart_data[3]; state <= state + 1'd1; end 6: begin tx <= uart_data[4]; state <= state + 1'd1; end 7: begin tx <= uart_data[5]; state <= state + 1'd1; end 8: begin tx <= uart_data[6]; state <= state + 1'd1; end 9: begin tx <= uart_data[7]; state <= state + 1'd1; end default: begin tx <= 1'd1; if(~hz_1) state <= 4'd0; end endcase end always @(posedge hz_1) begin case(letter) 0:uart_data <= "b"; 1:uart_data <= "l"; 2:uart_data <= "o"; 3:uart_data <= "g"; 4:uart_data <= "."; 5:uart_data <= "j"; 6:uart_data <= "c"; 7:uart_data <= "o"; 8:uart_data <= "r"; 9:uart_data <= "p"; 10:uart_data <= "."; 11:uart_data <= "r"; 12:uart_data <= "u"; 13:uart_data <= " "; 14:uart_data <= "\n"; 15:uart_data <= "\r"; endcase letter <= letter + 1'd1; end endmodule |
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